Project architecture

Fig. 1 Structure of project files.

IP cores under test are wrapped in Python adaptation code using LiteX. This provides a unified interface for other parts of the testbench. The wrapper code for the whole system is translated to Verilog for simulation. For communication with the simulator cocotb module is used. Expected descriptor values are stored in a human-readable JSON format.

Repository structure

Main repository for the project that gathers needed dependencies is usb-test-suite-build. Project code lives in two repositories:

usb-test-suite-cocotb-usb

This repository contains functions for triggering and verifying USB transfers from host side, packaged as a Python module.

usb-test-suite-testbenches

In this repository the test cases are stored, along with configuration and wrapper files for supported IP cores.

Other submodules

• LiteX - used to write the wrapper system in Python
• yosys - provides simulation libs for some of the targets
• repositiories of the tested submodules