Supported targets

ValentyUSB IP core

CPU-less target with eptri interface written in LiteX.

usb1_device

A USB1.1 IP core developed by asics.ws in Verilog.

Foboot

Target with VexRiscV CPU running bare-metal Foboot firmware. It utilizes epfifo interface of ValentyUSB core.

TinyFPGA-Bootloader

IP core written in Verilog with interesting features, like providing an interface to program SPI flash memory over USB.

tnt`s USB IP core

Target with a picorv32 CPU, running bare-metal firmware interfacing with Verilog IP core.